Coincident gate delivery device for use in the automatic recognition of symbols



Oct. 11, 1966 K. SCHEIDHAUER ETAL 3,

DEVICE FOR USE IN THE AUTOMATIC RECOGNITION OF SYMBOLS Filed March 16, 1964 DISCR/M/NATOR I 0 l l /-1-TRANSDUCER DELAY LINE 2!; J3 w A A M1 M3 POLAR/TY INVERTER Pi 4 0 1 I T COINCIDENCE GATES ""w '1r ""1 (I; H Ei- ESTORAGE MEANS LE II J;F LJII =+I EJ T CO/NC/DENCE GATES A/ IL T R R? INTEGRATING I CORRELATION AMPLIFIER 5 NETwORK /t I i INvENToRs Kurt scheidhouega Heinz Kusc L N Q Wwm/ ATTORNEYS United States Patent 6 Claims. (C1,. 340-1463) The present invention relates generally to the scanning art, and, more particularly, to character recognition arrangements for the proper identification of symbols or characters which are automatically scanned.

Arrangements for the automatic identification of char. acters are knOWn in which voltage wave forms are produced by the scanning of the symbols through a slot, for example, the gap of a magnetic head. Characteristics of the individual symbols are utilized in such a manner that several discrete voltages are selected from the curve of the wave forms and these voltages appear at certain loca tions spaced from one another at certain distances along the wave forms. It is customary to feed the Wave forms to a delay line provided with tapping points so that the several discrete voltages can be used. A delay line which is balanced with respect to ground can be used (for providing the voltages, but with this construction the voltage of opposite polarity is also obtained. The voltages are fed to correlation networks each of which corresponds to a given symbol. These networks are provided with resistors and under certain circumstances provide comparative voltages and make identification of the corresponding wave form possible.

The correlation networks are connected in parallel to a number of inputs. The number of inputs corresponds to the number of voltages which are to be evaluated. The scanning of these voltages with simultaneous feeding of the voltages or voltages proportional thereto into the inputs of the correlation networks is carried out at a particular instant. This instant is that at which the wave form in the delay line is at a certain reference position in which characteristic points of the wave form, and particularly amplitude peaks-but under certain circumstances also points of voltage reversalappear at these tapping points. This reference instant is obtained from that instant at which the first steep voltage rise occurs because of the passage of the front edge of the symbol across the slot, it being noted that this edge is parallel to the slot. The above-referred to reference instant is a certain time interval later than the time of arrival of the front flank of the symbol wave.

There is a certain relative speed between the scanning slot and the symbol carrier and this is the prerequisite for having the characteristic points of the wave to be evaluated positioned in front of the tapping points distributed along the breadth of the wave exactly at the references instant. Also, the time interval from the arrival of the front flank of the symbol wave until the wave form attains its reference position i dependent upon this speed.

Because of this, high standards of accuracy with which the relative speed is to be maintained must be fulfilled. Deviations of the speed beyond the narrow limits of allowable tolerance would mean that at the reference instant, the correct points of the wave form are not present and thus the peak points will not be disposed in front of the tapping points. This can also occur due to variations in the breadth of the symbols.

With these defects of the prior art in mind, it is a main object of the present invention to eliminate the above-mentioned shortcomings of the prior art and to provide larger tolerances in a circuit arrangement.

Another object of the invention is to provide a device of the character described wherein sets of gates are used for aiding in the provision of the proper timing.

These objects and others ancillary thereto are accomplished in accordance with preferred embodiments of the invention wherein storage means for the voltages and the inputs of the correlation networks assigned to the tapping points, and for example condensors are used. Preferably, gates are connected before the storage means and these are opened for those time intervals at which partial sections of the wave form are passing through. Further gates are connected behind the storage means and these further gates are opened for a transient moment of time after the storage means have been charged for transmitting the voltages to the correlation networks.

Additional objects and advantages of the present invention will become apparent upon consideration of the following description when taken in conjunction with the accompanying drawing in which the sole figure of the drawing is a block diagram showing the present invention.

It should be noted that the present description refers to circuitry some of which is disclosed in further detail in copending application Serial No. 232,693, filed October 24, 1962. Also, U.S. Patent No. 2,924,812 as well as U.S. Patent No. 3,000,000 are concerned with the character recognition art and teach how character recognition is effected.

With more particular reference to the present drawing, a delay line DL is provided and the wave form is fed to this delay line at input 15,, which may be the output of a transducer. A plurality of tapping points A are provided along the delay line but only four of these tapping points are illustrated in the drawing. An exemplary form W of a section of a symbol characteristic wave which pertains to the four tapping points in the reference position is shown above the delay line. If desired, a polarity inverter stage Pi may be connected after the tapping points. The voltages of one polarity are inverted in this stage so that all tapped voltages of the individual tapping points are brought to the same polarity.

Each of the voltages which pertains to a tapping point A appears at an input of a coincidence or AND-gate T which is assigned to or correlated with this tapping point. Storage means in the form of capacitors C are connected to the output of each gate T A discharge line is connected from each capacitor C to the input of a further set of AND-gates T each of which pertains to a particular capacitor. The outputs of these gates T are connected with the inputs E of the correlation networks, one of which is schematically indicated by the box formed by the dashed line K. The correlation network may, for example, be provided with resistors R having a resistance which is adapted to the assigned wave form. These resistors are on the one hand connected in series to respectively one input point B, and, on the other band, are connected together to an integrating amplifier S.

In the previously customary scanning operation, the voltages at tapping points A were scanned at a certain reference instant, as described above, and they were then fed immediately to the correlation networks. The reference instant is assumed to be that instant at which the peaks of the wave form W are disposed on the ordinates which pertain to the tapping points as illustrated in the drawing. It should be realized that if this is not the case and the peaks are disposed beside the ordinates due to, for example, inaccuracy in speed, substantially different voltage values will be provided and proper identification is endangered.

In the illustrated circuit arrangement in accordance with the present invention, the gates T are controlled in such a manner that they are all opened or readied for the passage of a signal therethrough at an instant which is prior to that instant at which the passing of the characteristic points through the tapping points is to be expected.

All of these gates are maintained open for a time interval having a duration which assures that the characteristic points have passed the tapping points'during this interval. During this period of time the capacitors C are correspondingly charged, that is, particularly in proportion to the peak voltage which has occurred.

Subsequent to the above-mentioned time interval, the gates T are opened, and they are maintained open at a time interval which is suflicient to assure that during this interval the capacitors C may discharge and the stored voltages can be applied to the inputs of the correlation networks.

Preferably, the instant of arrival of the front flank of a symbol is used as the starting instant for controlling the gates. A discriminator D provides a pulse when the voltage rise is produced by the front edge of the symbol. This pulse activates a first monostable flip-flop M which changes back to its original condition after a predetermined period of time. The end of this period of time 'occurs at an instant shortly before passage of the char.-

acteristic points which are expected. When M changes to its original condition, a second monostable flip-flop M is activated which also remains in its unstable state for a predetermined period of time. During this period of time it delivers a potential to the gates T which opens the gates so that signals from the polarity inverter Pi can pass through the gates.

This pulse which is emitted by the discriminator D is also applied to the input of another monostable flip-flop M which also changes back to its original condition after a predetermined period of time which is longer than the sum of the inherent or characteristic times of M and M that is, it changes back to its original condition at an instant at which the storage capacitors C are charged and the gates T are again closed. As it changes back to its original condition, M activates a monostable flipflop M which, in turn, applies a voltage to open the gates T during the time M is in its unstable condition. This inherent or characteristic time for M is designed so that the time interval that the gates T are opened ensures the delivery to the correlation networks of the voltages which are stored in the capacitors, in a manner as discussed above.

It will be understood that the above description of the present invention is susceptible to various modifications, changes, and adaptations, and the same are intended to be comprehended within the meaning and range of equivalents of the appended claims.

What is claimed is:

1. In an arrangement for recognizing symbols each of which is capable of providing a transducer with a different wave form and having a transducer for scanning the symbols for generating a different electrical energy wave form for each symbol and delay means connected to the transducer, the improvement comprising:

a set of correlation networks for recognizing a set of voltages characteristic of a particular symbol and having inputs;

a plurality of tapping points on said delay means;

storage means connected between said tapping points and the inputs to said correlation networks;

a set of first coincidence gate means connected before the storage means and arranged to be opened for time intervals during which certain sections of the wave forms pass through; and

a second set of coincidence gate means connected after the storage means and arranged to be opened for a short period of time after the storage means have been charged for feeding the voltages to the correlation networks.

2. An arrangement as defined in claim 1 wherein said storage means are capacitors.

3. A device for recognizing symbols, of a set of symbols, each capable of providing a transducer with a differ ent Wave form, said device comprising, in combination:

(a) transducer means for scanning symbols of a set of symbols for generating a dilferent electrical energy wave form for each symbol;

(b) delay line means connected to said transducer and having a plurality of output tapping points therealong;

(c) a first set of coincidence gate means having one respective input connected to a respective tapping point;

(d) a set of storage means each connected to the respective output of a coincidence gate means for storing the electrical energy at the respective tapping point at a particular instant;

(e) a second set of coincidence gate means having one respective input connected to a respective storage means;

(f) correlation network means connected to receive the respective outputs of said second set of coincidence means;

(g) discriminator means connected for detecting the beginning of a wave form entering said delay line means;

(h) first monostable flip-flop means connected to be placed into its unstable condition when said discriminator means detects a wave form in said delay line means and for remaining in its unstable condition until a period of time just prior to said particular instant when it changes back to its original stable condition;

(i) second monostable flip-flop means connected between the output of said first flip-flop means and the other inputs of said first set of coincidence gate means for unblocking the latter ,during the time said second flip-flop means is in its unstable condition which is initiated by the return of said first flip-flop means to its original condition;

(3') third monostable flip-flop means connected to be placed into its unstable condition when said discriminator means detects a wave form in said delay line means and for remaining in its unstable'condition for a period of timeat least as long as the sum of the time periods during which said first and second means are in their unstable condition; and

(k) fourth monostable flip-flop means connected between the output of said third flip-flop means and the other inputs of said second set of coincidence gate means for unblocking the latter while said fourth flip-flop means is in its unstable condition which is initiated by the return of said third flipflop means to its original c0nditi0n.. i

4. A device as defined in claim -3 comprising polarity inverter means connected between said tapping points and said first set of coincidence gate means.

5. A device for recognizing symbols of a set of symbols, each capable of providing a transducer with a different wave form, said device comprising, in combination:

(a) transducer means for scanning symbols of a set of symbols for generating a different electrical energy wave form for each symbol;

(b) delay line means connected to said transducer and having a plurality of output tapping points therealong;

(c) a first set of coincidence gate means having one respective input connected to a respective tapping point;

((1) a set of storage means each connected to the respective output of a coincidence gate means for storing the electriical energy at the respective tapping point at 'a particular instant;

(e) a second set of coincidence gate means having one ing the beginning of a wave form entering said delay line respective input connected to the output of a remeans.

spective storage means; References Cited by the Examiner th'i i fiiiififiiioifi 2? 51 i fii if i? 5 UNITED STATES PATENTS 1 1 e n p S Ce m 3,111,647 11/1963 Helzer 340-146.3 3 142824 7/1964 Hill 340146 3 1 t t t (g) t1m1ng means connec ed 0 de ect the entry of a 3,188,611 6/1965 Perotto 340-1463 wave form into said delay line means and for unblocking said first set of gate means just prior to FOREIGN PATENTS said particular instant and for unblocking said sec- 10 916 305 1/1963 Great Britain and set of gate means after said particular instant and when said first set of gate means are in blocked MAYNARD WILBUR, primary Examiner condition. 6. A device as defined in claim 5 wherein said timing MALCOLM MORRISON Exammer' means include discriminator means connected for detect- 15 I. E, SMITH, Assistant Examiner. 

5. A DEVICE FOR RECOGNIZING SYMBOLS OF A SET OF SYMBOLS, EACH CAPABLE OF PROVIDING A TRANSDUCER WITH A DIFFERENT WAVE FORM, SAID DEVICE COMPRISING, IN COMBINATION: (A) TRANSDUCER MEANS FOR SCANNING SYMBOLS OF A SET OF SYMBOLS FOR GENERATING A DIFFERENT ELECTRICAL ENERGY WAVE FORM FOR EACH SYMBOL; (B) DELAY LINE MEANS CONNECTED TO SAID TRANSDUCER AND HAVING A PLURALITY OF OUTPUT TAPPING POINTS THEREALONG; (C) A FIRST SET OF COINCIDENCE GATE MEANS HAVING ONE RESPECTIVE INPUT CONNECTED TO A RESPECTIVE TAPPING POINT; (D) A SET OF STORAGE MEANS EACH CONNECTED TO THE RESPECTIVE OUTPUT OF COINCIDENCE GATE MEANS FOR STORING THE ELECTRICAL ENERGY AT THE RESPECTIVE TAPPING POINT AT A PARTICULAR INSTANT; (E) A SECOND SET OF COINCIDENCE GATE MEANS HAVING ONE RESPECTIVE INPUT CONNECTED TO THE OUTPUT OF A RESPECTIVE STORAGE MEANS; (F) CORRELATION NETWORK MEANS CONNECTED TO RECEIVE THE OUTPUTS OF SAID SECOND SET OF COINCIDENCE MEANS; AND (G) TIMING MEANS CONNECTED TO DETECT THE ENTRY OF A WAVE FORM INTO SAID DELAY LINE MEANS AND FOR UNBLOCKING SAID FIRST SET OF GATE MEANS JUST PRIOR TO SAID PARTICULAR INSTANT AND FOR UNBLOCKING SAID SECOND SET OF GATE MEANS AFTER SAID PARTICULAR INSTANT AND WHEN SAID FIRST SET OF GATE MEANS ARE IN BLOCKED CONDITION. 